1. Field of the Invention
The present invention relates to a semiconductor integrated circuit for outputting video signals to a display device or the like and, more particularly, to a semiconductor integrated circuit with an improved format in which the video signals are composed.
2. Description of the Background Art
Some video signals that are output to a display device or the like have different frame frequencies (i.e., number of frames output per unit time). A progressive digital image of the NTSC system has 450,450 pixels (=525 linesxc3x97858 pixels) per frame output from a semiconductor integrated circuit in synchronism with a clock at a frequency of 27 MHz. In this case, the frame frequency for the progressive digital image of the NTSC system is given as 27xc3x97106/450,450=59.94 Hz. Meanwhile, a progressive digital image according to the digital television system usually has a frame frequency of 60 Hz. If that digital image is to have 450,450 pixels (=525 linesxc3x97858 pixels) per frame, then these pixels need to be output in synchronism with a clock at a frequency of 27.027 MHz.
Semiconductor integrated circuits capable of outputting a plurality of types of digital images at different frame frequencies are for general purpose use and are now in increasing demand. Such a semiconductor integrated circuit requires preparing a plurality of clocks having different frequencies: a 27 MHz clock for the NTSC system and a 27.027 MHz clock for the digital television system. Using a plurality of oscillators to provide clocks of different frequencies necessarily makes an entire image output system more costly than before. It is thus preferred to have a semiconductor integrated circuit that will operate on a single oscillator regardless of the frame frequency of the video signal in use. One such semiconductor integrated circuit is disclosed illustratively in Japanese Patent Laid-open No. Hei 8-65664.
According to FIG. 11 of the cited patent application, the disclosed semiconductor integrated circuit generates a video signal of 450,450 pixels (=525 linesxc3x97858 pixels) per frame with a field frequency of 29.97 Hz and of 450,000 pixels per frame with a field frequency of 30 Hz. The number of pixels per frame may be reduced for the field frequency of 30 Hz, which permits the use of a common 13.5 MHz clock. Where the field frequency is 30 Hz, lines 0 through 261 have 858 pixels each and line 262 has 632 pixels in a first field. In a second field, lines 263 through 523 have 858 pixels each and line 524 has 632 pixels. The two lines have a considerably reduced number of pixels each compared with the other lines. This triggers significant changes in horizontal scanning frequencies of the two lines when they are scanned.
Having a marked change in horizontal scanning frequency is detrimental to displaying an image on a display device. In particular, the marked change is not suitable in cases where the display device is equipped with a PLL (phase locked loop) circuit to receive a horizontal synchronizing signal reflecting a horizontal scanning frequency in order to reestablish synchronization in the horizontal direction based on that horizontal synchronizing signal. In such cases, an abrupt change in horizontal scanning frequency causes an unlock of the PLL circuit. Once the PLL circuit is unlocked, it takes time for the circuit to return to its locked state. This can result in a disturbed image on the display device.
It is therefore an object of the present invention to provide a semiconductor integrated circuit which, during display of a video signal entailing changes in the number of pixels between lines, outputs a video signal minimizing adverse effects on the image to be displayed on a display device.
It is another object of the invention to provide a semiconductor integrated circuit capable of modifying a format in which video signals are composed.
It is a further object of this invention to provide a specific constitution of a semiconductor integrated circuit conducive to implementing the above objects of the present invention.
The above objects of the present invention are achieved by a semiconductor integrated circuit for outputting a first video signal which corresponds to a screen and which has a plurality of pixels on each of a plurality of lines constituting the screen. Part of the pixels are active pixels representing image portions to be displayed on a display device. The plurality of lines are divided into a plurality of line groups. Each of the groups includes at least two consecutive lines. The lines included in each group have the same number of pixels each. On the other hand, the number of pixels per line is made different between any adjacent two of the plurality of line groups. The plurality of line groups include a plurality of line groups excluding lines having the active pixels.
The above objects of the present invention are also achieved by a semiconductor integrated circuit for outputting a video signal which corresponds to a screen and which has a plurality of pixels on each of a plurality of lines constituting the screen. Part of the pixels are active pixels representing image portions to be displayed on a display device. The semiconductor integrated circuit includes a plurality of first registers. The plurality of lines are divided into a plurality of line groups each including at least two lines. The lines included in each group have the same number of pixels each, while the number of pixels per line is made different between any adjacent two of the plurality of line groups. The number of lines included in each of the plurality of line groups is determined based on values placed in the plurality of first registers.
The above objects of the present invention are achieved by a semiconductor integrated circuit for outputting in synchronism with a clock signal a video signal which corresponds to a screen and which has a plurality of pixels on each of a plurality of lines constituting the screen. The semiconductor integrated circuit includes a pixel counter for counting up the clock signal in order to output a pixel number on each line. A comparator is provided for comparing a count value of the pixel counter with a comparative value. A line counter is further provided for counting up a match signal output by the comparator in order to output a line number. The semiconductor integrated circuit also includes a controller for supplying the comparative value to the comparator. The controller includes a plurality of decision circuits for which mutually exclusive ranges are established and which judge whether a count value of the line counter falls within any one of the established ranges. The controller further includes a first selector which receives a plurality of mutually exclusive values and selects one of the values in accordance with the judgments by the plurality of decision circuits. The selected value is output as the comparative value to the comparator.
Other objects and further features of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings.